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A 0.37μW 4bit 1MS/s SAR ADC for ultra-low energy radios

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5 Author(s)
Harpe, P. ; Holst Centre, IMEC, Eindhoven, Netherlands ; Huang, X. ; Xiaoyan Wang ; Dolmans, G.
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This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37μW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.

Published in:

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Date of Conference:

25-28 April 2011