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A high-level current model for macro cells using dynamic levelization algorithm

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4 Author(s)
Mu-Shun Matt Lee ; Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan ; Wei-Ting Liao ; Guan-Ming Zhu ; Liu, C.-N.J.

Since the power integrity problem has become one of the critical issues that limit the design performance, it is essential to obtain the supply current waveforms at early design stages to make efficient reduction of the supply noise. Therefore, a high-level macro current model is proposed in for logic blocks to provide quick current waveform estimation at RTL. However, due to the different arrival time of internal signals, it is not easy to accurately model the supply current of the whole logic blocks as some fixed templates. Therefore, a levelized high-level current model is proposed in this work for macro blocks. By grouping those gates with similar arrival time as a super-gate, the current waveform of this super-gate can be recorded easily with less error. Then, combining all triangles of every super-gate in time obtains a more accurate supply current waveform, especially for multi-peak cases. In order to consider the different arrival time of different input patterns, a dynamic levelization algorithm is also proposed. As shown in the experimental results, the average peak error of the proposed levelized current model is improved by almost 23% compared to the conventional single-stage current model.

Published in:

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Date of Conference:

25-28 April 2011