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Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget

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2 Author(s)
Shu-Han Whi ; Nat. Chicao Tung Univ., Hsinchu, Taiwan ; Yu-Min Lee

Few of existing works on power reduction in 3D ICs discuss the ability of supply voltage scaling techniques for power optimization. In this work, a supply voltage assignment based method for minimizing the power consumption of 3D ICs is presented. The proposed approach includes three major headings: (1) 3D IC Voltage Assignment for power reduction with including three factors-sensitivity, proximity effect and level shifter (LS) budget; (2) 3D Electro-Thermal Analysis for the temperature distribution of 3D IC; (3) Thermal Aware Static Timing Analysis for thermal-related delay values of functional gates. The experimental results have shown a great power reduction by the proposed method.

Published in:

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Date of Conference:

25-28 April 2011

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