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Low power and area efficient semi-digital PLL for low bandwidth applications

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2 Author(s)
Dietl, M. ; Clock & Timing Products, Texas Instrum., Freising, Germany ; Sareen, P.

Conventional low bandwidth Phase lock loop uses an external Capacitor together with a big on chip ripple capacitor. A new architecture of a Phase lock loop is proposed which eliminates the need for an external capacitor. Also the value of the on chip capacitor is reduced drastically, reducing the chip size. The PLL architecture proposed uses very low power.

Published in:

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Date of Conference:

25-28 April 2011

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