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Comparative analysis of flip-flop designs for soft errors at advanced technology nodes

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9 Author(s)
B. L. Bhuva ; Vanderbilt University, Nashville, TN 37235, USA ; K. Lilja ; J. Holts ; S. -J. Wen
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For advanced fabrication technology nodes, novel single-event related failures are being observed. This paper details efforts to use 3D TCAD simulations to model these failure mechanisms and develop mitigation techniques for flip-flop designs. Simulation, as well as experimental, results are used to show validity of such an approach for future CMOS technologies.

Published in:

2011 IEEE International Conference on IC Design & Technology

Date of Conference:

2-4 May 2011