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In this paper, we estimate the influences of random dopants (RDs) and interface traps (ITs) using experimentally calibrated 3D device simulation on electrical characteristics of high-κ / metal gate CMOS devices. Statistically random devices with 2D ITs between the interface of silicon and HfO2 film as well as 3D RDs inside the device channel are simulated. Fluctuations of threshold voltage and on-/off-state current for devices with different effective oxide thickness of insulator film are analyzed and discussed. The engineering findings significantly indicate that RDs and ITs govern characteristics, respectively, are statistically correlate to each other and RDs dominate device's variability, compared with the influence of ITs; however, the influence degree varies with IT's number, density and position. The effect of RDs and ITs on device characteristic should be considered together properly. Notably, the position of ITs and RDs results in very different fluctuation in spite of the same number of ITs and RDs.