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Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

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2 Author(s)
Po-Yen Chiu ; Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan ; Ming-Dou Ker

A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25°C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.

Published in:

2011 IEEE International Conference on IC Design & Technology

Date of Conference:

2-4 May 2011