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Probabilistic equivalence checking based on high-level decision diagrams

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4 Author(s)
Karputkin, A. ; Tallinn Univ. of Technol., Tallinn, Estonia ; Ubar, R. ; Tombak, M. ; Raik, J.

The paper proposes a novel method for probabilistic equivalence checking of digital systems. The method is based on representing the high-level decision diagrams as the model of digital systems by the sets of characteristic polynomials. It is shown that this representation is canonical, i.e. the sets of polynomials for equivalent diagrams are the same up to the names of the variables. However, computing the full set of polynomials is unfeasible for large diagrams as it demands checking all assignments to the control variables. In order to cope with this problem we have developed a polynomial algorithm for probabilistic equivalence checking.

Published in:

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on

Date of Conference:

13-15 April 2011