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A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology

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3 Author(s)
Kopanski, J. ; Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland ; Pleskacz, W.A. ; Pienkowski, D.

In this paper a 5Gb/s equalizer has been presented. It is designed to operate within USB 3.0 transceiver and compensates for frequency dependent losses introduced by transmission channel. For the reference signal, the clock and data recovery circuit has been used. This approach allowed to minimize the equalizer components. Critical equalizer building blocks have been implemented in GLOBALFOUNDRIES 65 nm Low Power CMOS technology. Other blocks are modeled in hardware description language. Mixed-signal system simulation results show full functionality of the proposed solution.

Published in:

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on

Date of Conference:

13-15 April 2011