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An analog perspective on device reliability in 32nm high-κ metal gate technology

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4 Author(s)
Chouard, F.R. ; Lehrstuhl fur Tech. Elektron., Tech. Univ. Munchen, München, Germany ; More, S. ; Fulde, M. ; Schmitt-Landsiedel, D.

An assessment on analog circuit reliability for an advanced 32nm high-κ metal gate technology is given from the analog designer's point of view. Selected analog circuit blocks are investigated with respect to device stress states. A custom test structure, designed to reveal analog related device characteristics including relaxation effects, was used to perform stress measurements. In addition to common aging in inversion mode, degradation in accumulation mode is determined. Experiments reveal that relaxation shows a large variety in drift behavior, and degradation induced variations - even for analog size devices - can reach significant values. Both topics are main issues for analog circuits design. Thereupon a general approach to consider device aging for analog circuit reliability is proposed.

Published in:

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on

Date of Conference:

13-15 April 2011