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Design-for-Test method for high-speed ADCs: Behavioral description and optimization

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4 Author(s)
Lechuga, Y. ; Microelectron. Eng. Group, Univ. of Cantabria, Santander, Spain ; Mozuelos, R. ; Martinez, M. ; Bracho, S.

This paper presents a Design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. Then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.

Published in:

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on

Date of Conference:

13-15 April 2011