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Three-dimensional integrated circuits (3D ICs) promise to overcome barriers in interconnect scaling, thereby offering an opportunity to get higher performance using CMOS technology. Despite these benefits, testing remains a major obstacle that hinders the adoption of 3D integration. Test techniques and design-for-testability (DfT) solutions for 3D ICs have remained largely unexplored in the research community, even though experts in industry have identified a number of test challenges related to the lack of probe access for wafers, test access to modules in stacked wafers/dies, thermal concerns, test economics, and new defects arising from unique processing steps such as wafer thinning, alignment, and bonding. In this embedded tutorial, the speaker will present an overview of 3D integration, its unique processing and assembly steps, testing and DfT challenges, and some of the solutions being advocated for these challenges. The speaker will focus on proposals for pre-bond testing of dies and TSVs, DfT innovations related to the optimization of die wrappers, test scheduling solutions, and access to dies and inter-die interconnects during stack testing. Time permitting, the speaker will also highlight recent work on comprehensive cost modeling for 3D ICs, which includes the cost of design, manufacture, testing, and test flows.
Date of Conference: 13-15 April 2011