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For decades, Moore's law transistor cost scaling created a vibrant ecosystem of foundries, fabless design houses, IDMs, and suppliers. Each of these parties shared in the abundant economic benefits of the transistor cost scaling enabled by Moore's law. This led to specialization within each layer and vertical segment of the supply chain wherein rigid technical interfaces allowed unidimensional technology trajectories to thrive. As we approach the challenges of achieving economic scaling at 22nm and beyond, we are confronted with a new set of challenges that will require tighter integration along historically rigid interfaces. This environment sets the stage for the pendulum to swing toward technologies that take advantage of tighter coupling between layout architectures and process capabilities, and between process control needs and product sensitivities. Taking the next step in Moore's law with the application of smarter and more efficient circuit, layout, and lithography co-design techniques that can provide high density and increased yields at a sustainable cost. The key enabler of this methodology is the creation of a regular design fabric onto which one can efficiently map the selected templates using a limited number of printability-friendly layout patterns. The co-optimization of circuit, layout, and process is achieved by co-developing circuit functions, layout pattern library and lithography solutions. This solution replaces design rules for logic with a rigorously characterized set of layout Templates. We will demonstrate that this methodology will enable future technology nodes that utilize current generation lithography while minimizing the cost per good die. In particular, we will: discuss the choice of regular design fabrics and their implications on design metrics, yields and cost; show that the selection of circuit topologies can be mapped efficiently to the choice of regular design fabric, and compare lithography solutions such as double patterni- - ng (DPT), direct write multi-e-beam (MEBM) and interference lithography (IL) for the 22nm technology node and beyond.