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Known-blocking. Synchronization method for reliable processor using TMR & DPR in SRAM FPGAs

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5 Author(s)
Morillo, A. ; APERT Group, Univ. of Basque Country, Spain ; Astarloa, A. ; Lazaro, J. ; Bidarte, U.
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The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial Reconfiguration (DPR) allows the development of coarse grain modularity architectures where the redundant module is a soft-core microprocessor or a more complex logical unit based in a processor. However, its main lack is a suitable synchronization method for the faulty module once it is reconfigured. This paper shows the trends on synchronization methods for systems that make use of TMR and DPR and proposes a new synchronization method based on a non blocking scheme.

Published in:

Programmable Logic (SPL), 2011 VII Southern Conference on

Date of Conference:

13-15 April 2011

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