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Custom FPGA-based micro-architecture for streaming computing

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2 Author(s)
Alves, J.C. ; FEUP/INESC-Porto, Porto, Portugal ; Diniz, P.C.

This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources.

Published in:

Programmable Logic (SPL), 2011 VII Southern Conference on

Date of Conference:

13-15 April 2011