By Topic

Customizable security-aware cache for FPGA-based soft processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kurek, M. ; Dept. of Comput., Imperial Coll. London, London, UK ; Ilkos, I. ; Luk, W.

This paper describes a security-aware cache targeting field programmable gate array (FPGA) technology. Our design is based on an architecture with a remapping table, which provides resilience against side-channel timing attacks. We show how this cache design can be optimised for FPGA re sources by an index decoder with content addressable memory structure, which can be customized to meet various requirements. We show, for the first time, how our security aware cache can be included in the Leon 3 processor, and its performance and resource usage are evaluated.

Published in:

Programmable Logic (SPL), 2011 VII Southern Conference on

Date of Conference:

13-15 April 2011