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FPGA implementation of two very low complexity LDPC decoders

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5 Author(s)
Moreira, J.C. ; Dept. de Electron., Univ. Nac. de Mar del Plata, Mar del Plata, Argentina ; Rabini, M. ; Gonzalez, C. ; Gayoso, C.
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Low-Density Parity-Check (LDPC) codes are very efficient error control codes that are being considered as part of many next generation communication systems. In this paper FPGA implementations of two low complexity decoders are presented. These two implementations operate over any kind of parity check matrix, (including those randomly generated, structurally generated, either systematic or non systematic) and can be parametrically performed for any code rate k/n. The proposed implementations are both of very low complexity, because they operate using only sums, subtracts and look-up tables. One of these decoders offers the advantage of not requiring the knowledge of the signal-to-noise ratio of the channel, as it usually happens to most of decoders for LDPC codes.

Published in:

Programmable Logic (SPL), 2011 VII Southern Conference on

Date of Conference:

13-15 April 2011

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