By Topic

High-Performance FPGA Implementation of Discrete Wavelet Transform for Image Processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Qijun Huang ; Dept. of Electron. Sci. & Technol., Wuhan Univ., Wuhan, China ; Yajuan Wang ; Sheng Chang

In this paper, two high-performance FPGA implementations of discrete wavelet transform (DWT) and relevant inverse discrete wavelet transform (IDWT) are proposed. At first, a DWT/IDWT aiming at a special wavelet (Daubechies 8 wavelet) is implemented. The maximum clock frequency of this design can respectively achieve 200MHz on an Altera Cyclone II platform - DE II development board, which is an obvious advantage, comparing with similar literatures. Besides that, a universal discrete wavelet transform is designed, in which the wavelet type and the order of DWT/IDWT can be changed. It is flexible and configurable for different applications. The maximum clock frequency of this universal discrete wavelet transform design can achieve 100MHz on the DE II development board. For optimization, distributed arithmetic, look-up table architecture and pipeline technology are employed in our design. Finally, through an image test, our design is verified efficient in hardware image processing based on wavelet transform theory.

Published in:

Photonics and Optoelectronics (SOPO), 2011 Symposium on

Date of Conference:

16-18 May 2011