By Topic

A Comparative Study of Surface-Roughness-Induced Variability in Silicon Nanowire and Double-Gate FETs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Cresti, A. ; Inst. de Microelectron., Electromagn. et Photonique, Lab. d''Hyperfreq. et de Caracterisation, Univ. Joseph Fourier, Grenoble, France ; Pala, M.G. ; Poli, S. ; Mouis, Mireille
more authors

We study the effect of surface roughness (SR) at the Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson-Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors.

Published in:

Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 8 )