By Topic

Analysis of propagation delays in high-speed VLSI circuits using a distributed line model

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Passlack ; Dept. of Phys., Tech. Univ., Dresden, East Germany ; M. Uhle ; H. Elschner

A scattering parameter-based homogeneous distributed-line model with arbitrary initial and boundary conditions is proposed and its implementation in a general-purpose circuit simulator supporting user functions is described. Using a GaAs 0.5-μm MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10 5) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T c superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:9 ,  Issue: 8 )