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Analysis of propagation delays in high-speed VLSI circuits using a distributed line model

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3 Author(s)
Passlack, M. ; Dept. of Phys., Tech. Univ., Dresden, East Germany ; Uhle, M. ; Elschner, H.

A scattering parameter-based homogeneous distributed-line model with arbitrary initial and boundary conditions is proposed and its implementation in a general-purpose circuit simulator supporting user functions is described. Using a GaAs 0.5-μm MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10 5) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T c superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 8 )