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Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays

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2 Author(s)
Nam Ling ; Dept. of Electr. Eng. & Comput. Sci., Santa Clara Univ., CA, USA ; Bayoumi, M.A.

A systolic temporal arithmetic (STA) formalism suitable for describing arithmetic operations in dynamic environments is introduced. It can be used for formal specification and verification of systolic arrays at the array architecture level. Besides providing value and operation abstraction from the lower level, it also exploits several features of systolic arrays, such as synchrony, regularity, repeatability, modularity, pipelinability, parallel processing ability, and spatial and temporal locality. STA provides constructs and verification techniques for simple, efficient, and effective systolic-array specification and verification. Verification techniques such as mathematical induction are suggested to exploit these systolic array features so as to speed up the process. STA overcomes several limitations of other existing specification and verification techniques and can be used with lower-level formalism for multilevel reasoning of systolic arrays. A brief description of this formalism and examples of how the formalism can be applied for formal specification and verification of two systolic arrays are discussed. Other applications of STA, such as simulations, fault diagnoses, and test generation for systolic arrays, are also suggested

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 8 )