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Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor

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3 Author(s)
Ishiura, N. ; Dept. of Inf. Sci., Kyoto Univ., Japan ; Ito, M. ; Yajima, S.

An approach to accelerating fault simulation using a vector super computer is described and the zero-delay, two-valued fault simulation of gate-level combinational circuits is discussed. As a vector processor oriented simulation technique, an algorithm was developed that is based on the parallel fault simulation technique. In the technique, fault simulation can be accelerated (given that enough vector lengths can be obtained) to a maximum of 20 times faster using vector operations of a currently available vector computer by extending the processing unit from one word to multiple words. However, when fault simulation to generate or to evaluate test patterns is performed, enough vector length is not obtained or the computation time increases if large vector length is attempted because detected faults are dropped. In order to address the problems, a dynamic, two-dimensional, parallel fault simulation technique is proposed. In this technique, large vector length is obtained by utilizing both fault and pattern parallelism, and fault dropping is efficiently used to adjusting the two parallelism factors complementarily from pass to pass. The computation time is further reduced by combining this technique with selective tracing under the notion of multiple fault propagation. The experiments on the FACOM vector processor show that the simulation speed is accelerated by 10 to about 15 times through vectorization

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 8 )