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Novel CMOS ternary flip-flops using double pass-transistor logic

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2 Author(s)
Guoqiang Hang ; Sch. of Inf. & Electr. Eng., Zhejiang Univ. City Coll., Hangzhou, China ; Xuanchang Zhou

Novel CMOS D-type and modular algebra-based edge-triggered ternary flip-flops using double pass-transistor logic(DPL), are presented. In the proposed circuit scheme, literal functions are also realized by using traditional MOS transistors without any modification of the thresholds. The DPL-based flip-flop has some favourable properties: perfectly symmetrical structure, full logic swing and the maximum possible noise margins, the less complex structure, and no static power consumption. The proposed D-type flip-flop consists of complementary inputs/outputs and is thus a dual rail ternary flip-flop. The modular algebra-based flip-flop can give triple-rail ternary complementary outputs. HSPICE simulations using 0.35μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design approach.

Published in:

Electric Information and Control Engineering (ICEICE), 2011 International Conference on

Date of Conference:

15-17 April 2011