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Computing signal delay in general RC networks by tree/link partitioning

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2 Author(s)
Chan, P.K. ; Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA ; Karplus, K.

Most RC simulators handle only tree networks, not arbitrary networks. An algorithm is presented for computing signal delays in general RC networks using the RC-tree computation as the primary operation. The algorithm partitions a given network into a spanning tree and links. It computes the signal delay of the spanning tree, and updates the signal delay as it incrementally adds the links back to reconstruct the original network. If m is the number of links, this algorithm requires m(m+1)/2 updates and m+1 tree delay evaluations. All the tree delay evaluations involve computing signal delays with the same resistive spanning tree, but with different values for the capacitors

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 8 )