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Design of Class-E Amplifier With MOSFET Linear Gate-to-Drain and Nonlinear Drain-to-Source Capacitances

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5 Author(s)
Xiuqin Wei ; Grad. Sch. of Adv. Integration Sci., Chiba Univ., Chiba, Japan ; Sekiya, H. ; Kuroiwa, S. ; Suetsugu, T.
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This paper presents expressions for the waveforms and design equations to satisfy the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Expressions are given for power output capability and power conversion efficiency. Design examples are presented along with the PSpice-simulation and experimental waveforms at 2.3 W output power and 4 MHz operating frequency. It is shown from the expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state affects the switch-voltage waveform. Therefore, it is necessary to consider the MOSFET gate-to-drain capacitance for achieving the class-E ZVS/ZDS conditions. As a result, the power output capability and the power conversion efficiency are also affected by the MOSFET gate-to-drain capacitance. The waveforms obtained from PSpice simulations and circuit experiments showed the quantitative agreements with the theoretical predictions, which verify the expressions given in this paper.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:58 ,  Issue: 10 )