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More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.