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Thermal-aware router-sharing architecture for 3D Network-on-Chip designs

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3 Author(s)
Yong-Ruei Huang ; Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Jia-Hong Pan ; Yi-Chang Lu

In this paper we propose a router-sharing architecture for 3D NoC which outperforms existing 3D NoC designs under thermal impacts. According to thermal simulations, in conventional designs, the routers on the top layers far from the heat sink have to be disabled frequently to avoid thermal emergency. Therefore, the proposed architecture removes all routers on the top layers and uses only buses to connect top-layer PEs to the routers underneath. At 85 °C, our architecture receives 1.4 times as many packets when compared to conventional designs. If the temperature constraint is set at 80 °C, our architecture can receive 2 times as many packets. In addition, this new architecture is energy-efficient because the average number of hops is reduced.

Published in:

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Date of Conference:

6-9 Dec. 2010

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