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Jitter generation and capture using phase-domain sigma-delta encoding

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3 Author(s)
Aouini, S. ; Integrated Microsyst. Lab., McGill Univ., Montreal, QC, Canada ; Kun Chuai ; Roberts, G.W.

This article presents techniques and circuits for jitter generation and measurement. The proposed implementations use periodic bit-streams and high-order PLLs to generate the desired phase signal. Here, an arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and converted to the phase-domain through a digital-to-time converter (DTC) process realized in software. The resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-domain filter. The parameters of the sigma-delta modulator along with those of the high-order PLL can be traded for one another to achieve maximum performance. The method to generate the sigma-delta encoded phase signal and to design the high-order PLL is presented. A high quality Gaussian jitter signal has been experimentally generated. Also, a setup using DC encoded phase shifts serving as an under-sampling clock to measure jitter with a 50 GHz effective sampling rate has also been experimentally proven. The conciseness and digital nature of the jitter generation scheme together with the jitter measurement architecture makes them easily amenable to a design-for-test framework.

Published in:

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Date of Conference:

6-9 Dec. 2010