By Topic

Low IR drop and low power parallel CAM design using gated power transistor technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Anh Tuan Do ; Sch. of EEE, Nanyang Technol. Univ., Singapore, Singapore ; Shoushun Chen ; Zhi-Hui Kong ; Kiat Seng Yeo

In this paper we analyzed the IR drop problem in large scale content addressable memory (CAM) and proposed a simple yet efficient gated power transistor technique. Each row of CAM cells is powered by two metal rails, one for the memory element and another one for the comparison transistors and the match lines. The latter rail is powered by a row-based transistor, which presents a physical “gate” to limit the peak current during comparison. Smart control scheme is proposed to automatically turn the power transistor off using a feedback delay loop. Simulation reports 96% reduction in IR drop and 64% save in total energy consumption, for a conceptual 8K-word CAM macros based on Chartered 0.13μm CMOS technology.

Published in:

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Date of Conference:

6-9 Dec. 2010