Performance evaluation of OFDM de-modulator with various multiplier architectures for UWB system

In this paper the effects of multiplier architecture on the overall performance of the OFDM De-modulator for an UWB system are studied. The two commonly used VLSI multiplication algorithms, namely, the Baugh-Wooley algorithm and the Modified-Booth algorithm, are the candidates for this study. Partial product accumulation session can be found in both algorithms. There are two major classes of partial product accumulation architectures which are the tree architecture and the array architecture. Under a specific speed that can meet the requirement of an UWB system, silicon usage, power consumption, and SQNR of the various architectures are compared. All OFDM de-modulators in this study are implemented with 0.13um CMOS technology and the multiplier used in the de-modulator is 10bits × 10 bits. Simulation results show that the tree type Baugh-Wooley multiplier with an output word-length of 12 bits can achieve the best balance between silicon usage, power consumption and SQNR.