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Low-Frequency Noise Investigation and Noise Variability Analysis in High- k /Metal Gate 32-nm CMOS Transistors

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5 Author(s)
Diana Lopez ; Institut de Microelectronique, Electromagnetisme et Photonique/Laboratoire d'Hyperfréquences et de Caractérisatio, Grenoble, France ; S. Haendler ; C. Leyris ; Gregory Bidal
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Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal-oxide-semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology.

Published in:

IEEE Transactions on Electron Devices  (Volume:58 ,  Issue: 8 )