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An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion

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4 Author(s)
Hiroshi Fuketa ; Institute of Industrial Science, University of Tokyo, Tokyo, Japan ; Dan Kuroda ; Masanori Hashimoto ; Takao Onoye

A self-timed subthreshold processor was developed in 65-nm complimentary metal-oxide-semiconductor process. This four-stage reduced instruction set computer processor synchronously operates with the memory read completion signal produced in 8.5-kb instruction and 2-kb data memories of subthreshold 10T static random-access memory. Measurement results show that the processor correctly functions from 0.56 to 0.36 V with a self-timed clock and achieves minimum energy per cycle of 3.47 pJ/cycle at 0.46-V supply voltage with 1.76-MHz average frequency. Compared with conventional synchronous operation with guardbanding, the proposed self-timed operation reduces the execution time of SHA-1 by 82% at 0.4-V supply voltage and saves energy by 40% to attain 1-MHz operation.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:58 ,  Issue: 5 )