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This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample rate is achieved through the use of fast open-loop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65 nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.