Leakage Reduction in Advanced Image Sensors Using an Improved ${\rm AB}^{2}{\rm C}$ Scheme

Static leakage currents in advanced CMOS processes have become the main source of power consumption in many of today's systems. This is especially true for systems with a large number of devices that are in a stable state for most of their operation time, such as image sensors and memory arrays. This paper introduces an improved adaptive bulk biasing control (AB
²
C) scheme for reduction of leakage currents during these “standby” periods in serially accessed arrays, while enabling device acceleration during active cycles. We provide a theoretical analysis of the AB
²
C operation, showing its advantages and limitations. The proposed scheme has been integrated with a test-case advanced wide dynamic range (WDR) image sensor with an on-chip memory. The scheme was applied to both the pixel and bitcell arrays, providing configurable leakage reduction and performance enhancement. An 80 nm test chip was fabricated with a 10 k pixel/bitcell test-case system and successfully tested, showing a 21% power reduction compared to a standard system and up to 44% compared to an accelerated system.