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FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities

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6 Author(s)
Will X. Y. Li ; Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong, China ; Ray C. C. Cheung ; Wei Zhang ; Rosa H. M. Chan
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We present a parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. The proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Accumulation) component, a second stage containing a pre-threshold potential updating unit with an error approximation function component, and a third stage consisting of a gradient calculation unit. A flexible and efficient architecture that can accommodate different design speed requirements are generated. Simulation results are rigorously analyzed. A hardware IP library for versatile models and applications is proposed. The design runs on a Xilinx Virtex-6 FPGA and the processing core produces data samples at a maximum clock rate of 357MHz, which is 4.37 × 105 times faster than the corresponding software model running on an AMD Pheono 9750 Quad Core Processor. It occupies 216,766 LUTs, maximum 12 block-RAMs, and 2016 DSP-blocks.

Published in:

Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on

Date of Conference:

1-3 May 2011