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Viability Study of All-III–V SRAM for Beyond-22-nm Logic Circuits

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2 Author(s)
Oh, S. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Wong, H.-S.P.

A physics-based compact model for III-V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak III-V PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-III-V SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 7 )