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Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing

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3 Author(s)
Supriyo Maji ; Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India ; Samiran Dam ; Pradip Mandal

This paper presents a new approach for generating saturation constraints and DC performance expressions for analog integrated circuits. It also proposes a generalized method to develop AC performance expressions of the same in posynomial form. The developed posynomial expressions can be used for well established geometric programming (GP) based sizing optimization. The equation generation method takes very less time and does not require any manual intervention. The proposed method for AC performance expression generation is built on two levels of abstraction of a circuit. At the higher level, referred as macromodel, circuit performance metrics are modeled as function of device parameters such as transconductance (gm), drain conductance (gd), small-signal parasitic capacitances and overdrive voltage (Vov). Whereas, at lower level of the abstraction the device parameters are monomial functions of device sizes and their biases. The two-level abstraction helps to develop technology independent performance model of a circuit. Whereas, the technology dependency is captured through device models. The proposed methods are applied to two well-known CMOS op-amp topologies namely, two-stage and folded-cascode to generate saturation constraints, DC and AC performance expressions. With the developed constraints, both the circuits are designed through GP based circuit optimization in a 0.18 μm UMC technology. Performances of both are verified at their final design points.

Published in:

Quality Electronic Design (ISQED), 2011 12th International Symposium on

Date of Conference:

14-16 March 2011