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Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control

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6 Author(s)

A system on a chip (SoC) is becoming smaller and denser. Shrinking transistor size facilitates the integration of functionality on the chip operating at low supply voltage, although this trend lowers the silicon chip reliability. Nevertheless, it is necessary to maintain complete functionality during a long duration, even under changing environments such as temperature fluctuation and/or device wearout: Bias temperature instability must be considered as a time-varying parameter as well. Consequently, techniques that can maintain chip reliability with self-diagnosis and self-repair capabilities are required. In this paper, we propose a dependable SRAM with a built-in self-test that can diagnose and repair itself using wordline and bitcell voltage control. The proposed SRAM comprises memory blocks; each block has independent supply voltages for the wordlines and bitcells. This diagnosis and repair scheme is especially effective for faults that occur in the field. The self-testing capability is available on-line. It is completely transparent to a user, who can use the SRAM with no modification or speed degradation in the memory access protocol. A 1-Mb (64-Kb × 16 blocks) SRAM with the BIST was fabricated with a 65-nm CMOS process and verified. The area overhead is 2.8%.

Published in:

Quality Electronic Design (ISQED), 2011 12th International Symposium on

Date of Conference:

14-16 March 2011