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Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously

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3 Author(s)
Li Li ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Ken Choi ; Nan, Haiqing

Clock gating and power gating are the two most widely used techniques to reduce dynamic power and leakage power respectively. It is desired that these two techniques can be integrated. In this paper, activity-driven optimized bus specific clock gating (OBSC) is applied to reduce dynamic power, and the enable signal generated by OBSC is used as the sleep signal for power gating. The power gated cells are determined by a proposed forward traversing algorithm. Moreover, minimum idle time concept is used to determine if the insertion of power gating will gain energy reduction. In order to evaluate our technique, ISCAS'89 circuits have been experimented. The simulation results prove that 25.07% dynamic power can be reduced by OBSC, and 45.12% active leakage power can be saved by power gating.

Published in:

Quality Electronic Design (ISQED), 2011 12th International Symposium on

Date of Conference:

14-16 March 2011