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Variation Tolerant AFPGA Architecture

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4 Author(s)
Hock Soon Low ; MSD Group, Newcastle Univ., Newcastle upon Tyne, UK ; Delong Shang ; Xia, F. ; Yakovlev, A.

This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets power supply variations, including modes such as dynamic voltage scaling and variable Vdd, such as in applications featuring energy harvesting. This is achieved by making the longer inter-block interconnects DI, keeping the computational logic single-rail, and removing global clocks.

Published in:

Asynchronous Circuits and Systems (ASYNC), 2011 17th IEEE International Symposium on

Date of Conference:

27-29 April 2011