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Improving Dependability and Performance of Fully Asynchronous On-chip Networks

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2 Author(s)
Imai, M. ; Univ. of Tokyo, Tokyo, Japan ; Yoneda, T.

Network-on-Chip (NoC) is now considered to be a promising approach to implementing many-core systems. In this paper, we propose fully asynchronous on-chip networks which have improved tolerance against stuck-at-faults, aging degradation faults and transient faults, as well as potential of high performance. We have developed a dependable routing algorithm to detour a faulty router or a faulty link based on local fault information. An adaptive routing algorithm based on local traffic load information is also used to achieve high performance. The proposed router circuits are based on the bundled-data method with MOUSETRAP-like transition signaling protocol, where programmable delay elements for the matched delays are used in order to tolerate static and dynamic delay variations. Duplicated control circuits for tolerating transient faults are also designed and evaluated. The LEDR (Level Encoded Dual Rail) encoding method is used in the link implementation to avoid the resetting phase overhead. The proposed on-chip networks are implemented using 130nm process technology for checking the correct functionality and evaluating performance.

Published in:

Asynchronous Circuits and Systems (ASYNC), 2011 17th IEEE International Symposium on

Date of Conference:

27-29 April 2011

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