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Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis

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2 Author(s)
Andrikos, N. ; Dept. of Electron. Eng., Politec. di Torino, Torino, Italy ; Lavagno, L.

High-level synthesis is becoming more and more popular in the recent years, since it increases the designers' productivity and allows for better optimizations at a higher level of abstraction. Its application to the asynchronous domain can combine the advantages of asynchronous design to result in additional performance gains. One of the most important parts of high-level synthesis is the scheduling problem. Since asynchronous circuits are not restricted to operating at multiples of the clock period, their scheduling can be more relaxed, allowing for greater performance gains. In this paper, we propose a novel formulation which transforms the scheduling problem to a Petri net. We then construct a reduced form of the state graph, which uses an appropriate very aggressive pruning in order to prevent the state explosion, but which still allows us to obtain the optimal scheduling. Our experiments verify the effectiveness of our methodology, which allows for scheduling even very large designs, without sacrificing optimality of the solution, while keeping run time lower than previous approaches.

Published in:

Asynchronous Circuits and Systems (ASYNC), 2011 17th IEEE International Symposium on

Date of Conference:

27-29 April 2011

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