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A systolic architecture for fast stack sequential decoders

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3 Author(s)
Lavoie, P. ; Dept. of Nat. Defence, Defence Res. Establ., Ottawa, Ont., Canada ; Haccoun, D. ; Savaria, Y.

The troublesome operation of reordering the stack in stack sequential decoders is alleviated by storing the nodes in a systolic priority queue that delivers the true top node in a short and constant amount of time. A new systolic priority queue is described that allows each decoding step, including retrieval, reordering and storage of the nodes, to take place in a single clock period. A complete decoder architecture designed around this queue is compared to a conventional stack-bucket architecture from both speed and cost points of view. The proposed decoder architecture appears to be faster, affordable, and compatible with convolutional codes having long memory and high coding rate

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Communications, IEEE Transactions on  (Volume:42 ,  Issue: 234 )