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Folding Memory Shared Processor Array (FMSPA) Architecture for Channel Estimation of Downlink OFDMA IEEE 802.16e System

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4 Author(s)
Savitri Galih ; Dept. of Inf., Widyatama Univ., Bandung, Indonesia ; Trio Adiono ; Adit Kurniawan ; Iskandar

The implementation of complex signal processing algorithms are required to achieve robust transmission, whereas mobile wireless application require low power dissipation. This paper describes an algorithm and a corresponding hardware architecture for the implementation of OFDMA 802.16e channel estimation. The advantage of the proposed architecture are low power and efficient resource utilization since we use iterative memory shared architecture that exploits reutilization of the processor elements and memory units. The higher data access scheme is utilized by scheduled memory sharing with common bus. Furthermore, we increase parallel efficiency by folding the architecture to reduce the number of processor elements.

Published in:

Parallel Computing in Electrical Engineering (PARELEC), 2011 6th International Symposium on

Date of Conference:

3-7 April 2011