Referenced Items are not available for this document.
The ongoing move of hardware platforms to many-core processor challenges the traditional software design methodology. It is critical to develop new programming paradigms and efficient ways to port legacy applications. This paper analyzed a typical packet processing application and also the cache hierarchy and behavior of Raw architecture many-core processor. It presented an easy to implement run-time dynamic core grouping approach to improve the system performance. This approach reduced the cache swap latency by grouping neighbor cores attached to the mesh network. It optimized the scale of group by experimental data got beforehand. The test results showed this approach can improve the Deep Packet Inspection (DPI) system performance around 10% with very minor code change.
Published in:
Parallel Computing in Electrical Engineering (PARELEC), 2011 6th International Symposium on
Date of Conference: 3-7 April 2011
- Page(s):
- 31 - 35
- E-ISBN :
- 978-0-7695-4397-0
- Print ISBN:
- 978-1-4577-0078-1
- INSPEC Accession Number:
- 12008167
- Conference Location :
- Luton
- Digital Object Identifier :
- 10.1109/PARELEC.2011.30
- Product Type:
- Conference Publications
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