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System-on-Wafer: 2-D and 3-D Technologies for Heterogeneous Systems

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7 Author(s)
Souriau, J.-C. ; Electron. & Inf. Technol. Lab., French Atomic Energy Comm., Grenoble, France ; Sillon, N. ; Brun, J. ; Boutry, H.
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System integration, performance, cost and enhanced product functionality form the major driving forces behind contemporary innovations in packaging. The need for miniaturization has led to new architectures which combine a whole range of different technologies. The ultimate miniaturization goal is to incorporate all of the elements necessary to build the system in the same package. This approach of system-in-package faces two critical issues: the management of components from different sources and the cost of individual operations necessary to complete the package. Taking into account all the developments that have been made to date on wafer level packaging (WLP), it has been proposed to perform the packaging system at wafer level. Fully tested bare dice are integrated onto or into a wafer which can be pre-processed and post-processed using techniques such as micromachining, passive integration, plating of via and pad redistribution, bumping, dicing and testing. The principal objective of this paper is to present alternative technology for integrated dice coming from various foundries where design, die thickness and contact pad metallurgy are predefined. System integration at wafer level is presented and discussed in this paper. Different approaches, such as system-on-wafer (SoW) or rebuilding a wafer, are introduced and a technology status report is drawn up.

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Components, Packaging and Manufacturing Technology, IEEE Transactions on  (Volume:1 ,  Issue: 6 )