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The entropy decoder proposed in this paper was implemented in VLSI (65nm process). It supports video decoding algorithms for three most popular video standards, H.264, AVS and MPEG-2. The decoding modules of H.264, AVS and MPEG-2 have some shared components, which greatly reduces the cost of hardware resources. Verification results showed that when exploiting a 200MHz working frequency, the entropy decoder can achieve 1080p@30fps for H.264, AVS and MPEG-2. This paper mainly focuses on the following aspects: the entropy decoder architecture and H.264, AVS and MPEG-2 decoding modules implementation.