Mapping deblocking algorithm of H.264 decoder onto a reconfigurable array architecture

This paper introduces several methods for mapping deblocking algorithm onto REconfigurable MUltimedia System (REMUS) processor, which consists of a general RISC processor and two Processing Element Arrays (PEAs). Although reconfigurable array architecture is efficient to computing-intensive tasks, which is difficult to implement control-intensive task, such as deblocking algorithm. In order to figure out this problem, RISC processor calculates several parameters and generate configuration information to determinate filter modes, PEAs accelerate regular computation due to parallelization and pipeline architecture. Compared to the deblocking execution on FloRA, XPP-III, deblocking algorithm on REMUS achieves the speedup of 79.2%, 34.74%, which compares to the implementation on FloRA and XPP-III architecture. Furthermore, those methods can be used for other algorithms to achieve acceleration, such as MC, IDCT.