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Notice of Retraction
Design of the time driving and image signal processing for linear CCD based on FPGA

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1 Author(s)
Zhao Yuan ; Eng. Coll., Chinese Armed Police Force, Xi'an, China

Notice of Retraction

After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.

The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.

A variety of driving pulse should be designed well in order that the linear CCD is working stable in image measuring, In this paper, in the base of analyzing the driving pulse and time sequence of TCD 1501D linear CCD, by analyzing the output image 0 signal of CCD, the paper gives out CDS circuit in and out of the CCD. At last, the required time sequence driving has been designed and the result has been simulated accurately by the use of development platform of Quartus II 7.2 combining with VHDL. The result of the simulation indicates that the driving circuit is characterized by simple framework, low power consumption, and strong anti-jamming ability, which meet the demand of miniaturization for the project.

Published in:

Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on

Date of Conference:

16-18 April 2011

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